1. Field of the Invention
This invention relates to adders and more particularly to a circuit and method in which a carry look-ahead adder is modified to support both adding and shifting of input bits.
2. Description of the Related Art
Microprocessors determine the speed and power of personal computers, and a growing number of more powerful machines, by handling most of the data processing in the machine. Microprocessors typically include at least three functional groups: the input output unit (I/O unit), the control unit, and the arithmetic-logic unit (ALU). The I/O unit interfaces between external circuitry and the ALU and the control unit. I/O units frequently include signal buffers for increasing the current capacity of a signal before the signal is sent to external components. The control unit controls the operation of the microprocessor by fetching instructions from the I/O unit and translating the instructions into a form that can be understood by the ALU. In addition, the control unit keeps track of which step of the program is being executed. The ALU handles the mathematical computations and logical operations that are performed by the microprocessor. The ALU executes the decoded instructions received from the control unit to modify data contained in registers within the microprocessor.
An essential component of any ALU is the adder circuit. The adder circuit performs addition operations on two or more input operands. Because the addition operation is one of the most commonly invoked operations during the execution of a computer program, the speed with which the adder circuit can compute the sum (or difference) of two input operands is extremely important in determining the speed of the overall system.
Several common adder circuits are well known in the field of digital logic A ripple-carry adder, for example, adds two (or possibly more) operands in much the same manner as a person would add two numbers The least significant bit of the first operand is added to the least significant bit of the second operand (and possibly a carry-in bit) to produce a least significant result bit and a least significant carry bit. The least significant carry bit is then added to the next most significant bit of the first operand and the next most significant bit of the second operand to produce a next most significant result bit and a next most significant carry bit. This sequence continues until, eventually, the most significant bits of the operands have been added together with the carry bit from the preceding stage to produce the most significant result bit and a carry-out bit. The carry-out bit of the ripple carry adder can be used as a carry-in bit to a subsequent adder circuit such that multiple ripple carry adders can be connected together in series.
Those skilled in the art of digital circuit design will appreciate that a least significant result bit is generated prior to an intermediate significant result bit which, in turn, is generated prior to a mast significant result bit. Therefore, there is a time delay between the generation of the least significant result bit and the most significant result bit. With each additional stage, the time delay between generation of the least significant result bit and the most significant result bit increases more or less linearly, negatively impacting the overall performance of the ALU, the microprocessor, and ultimately, the computing system as a whole.
It would be therefore be desirable to produce an adder circuit that achieves a significant reduction in the time required to produce a particular result without significantly increasing the amount of silicon required to implement the circuit and without significantly increasing the input loading. It would be even more desirable for the function of the produced adder circuit to subsume the function of another special-purpose circuit in the ALU, thereby allowing the special purpose circuit to be eliminated.